IP-блоки CAST для разработчиков СБИС

ООО Униведа работает с компанией CAST Inc. с 2011 года по договору о представительстве - см. ссылку на официальном сайте CAST:

Local Representatives
UnivEDA Co. Ltd.
Russia, Moscow, 125373,
b-r Yana Raynisa, d43, korp1, pomII, komn4, et2, of2/1v
Vitaly Kravchenko
T +7 985 999-7272
E-Mail: vitaly.kravchenko@univeda.ru

Компания CAST предлагает широкий выбор IP-блоков для проектирования СБИС и ПЛИС.

Весь список IP-блоков CAST можно найти ниже по тексту.

32-bit BA2X Processors
32-bit Basic Application Processor
PipelineZero 32-bit Embedded Processor
32-bit Low-Power Deeply Embedded Processor
32-bit Cache-Enabled Embedded Processor
32-bit Deeply Embedded Processor
32-bit Application Processor
Talos Evaluation Kit for BA2X Processor IP Cores
8051 Microcontrollers
Legacy-Configurable 8051-Compatible Microcontroller IP
High-Performance, Configurable, 8-bit Microcontroller
Super-Fast, Configurable 16-bit 80251 Microcontroller
Super-Fast 8051 Microcontroller with Configurable Features & Peripherals
Ultra-Small 8051-Compatible Microcontroller
Evaluation Kit for 8051 MCUs

GZIP Lossless Data Compression
GZIP & GUNZIP Acceleration Card Reference Design for Intel FPGAs
GZIP & GUNZIP Accelerator Reference Design for Xilinx FPGAs
GZIP/ZLIB/Deflate Data Compressor
GUNZIP/ZLIB/Inflate Data Decompression
AVC & HEVC Video Compression
Low-Latency AVC/H.264 Baseline Profile Decoder
Ultra-Fast AVC/H.264 Baseline Profile Encoder
Low-Power AVC/H.264 Baseline Profile Encoder
AVC/H.264 Video Encoder with Compressed Frame Store
H.264 High 10 Intra Profile Encoder
Low-Power AVC/H.264 Main Profile Encoder
Low-Power AVC/H.264 Baseline Profile Decoder
Hardware RTP Stack for H.264 Stream Encapsulation
H.264 Video Over IP – HD Decoder Subsystem
H.264 Video Over IP – HD Encoder Subsystem
HEVC/H.265 Main Profile Video Decoder
Hardware RTP Stack for H.264 Stream Decapsulation
JPEG & JPEG-LS Image Compression
Baseline JPEG Decoder
Ultra-Fast Baseline and Extended JPEG Decoder
Baseline and Extended JPEG Decoder
Baseline JPEG Encoder
Tiny Baseline JPEG Encoder
Ultra-Fast Baseline and Extended JPEG Encoder
Baseline and Extended JPEG Encoder
Lossless & Near-Lossless JPEG-LS Decoder
Lossless & Near-Lossless JPEG-LS Encoder
Hardware RTP Stack for JPEG Stream Encapsulation
Motion JPEG Over IP – HD Video Encoder Subsystem

Automotive Bus Controllers
CAN 2.0, CAN FD, and CAN XL Bus Controller
CAN2.0 & CAN-FD Verification IP
CAN-to-TSN Ethernet Gateway
CAN2.0 & CAN FD Reference Design
SENT/SAE J2716 Controller
LIN Bus Master/Slave Controller
LIN Verification IP
TSN Ethernet Endpoint Controller
TSN Ethernet Switched Endpoint Controller
TSN Ethernet Switch
TSN Ethernet Verification IP

Internet Protocol Stacks
Gigabit Ethernet Media Access Controller
Low-Latency 10/100/1000 Ethernet MAC
MPEG Transport Stream Multiplexing & Encapsulation Engine
TCP/IP - 1G/10Gbit Ethernet TCP Hardware Protocol Stack
100G UDP/IP Hardware Protocol Stack
10G/25G UDP/IP Hardware Protocol Stack
UDP/IP Hardware Protocol Stack
40G/50G UDP/IP Hardware Protocol Stack

MIPI I3C Basic Slave Controller
MIPI SPMI Master or Slave Controller

PCI - AMBA AHB Device/Host Bridge
32-bit/33MHz PCI Host Bridge
PCI to AMBA AHB Host Bridge
32-bit/33MHz PCI Master/Target
32-bit/33MHz Multi-Function PCI Master/Target
32-bit/33MHz PCI Target
32-bit/33MHz Multi-Function PCI Target

AHB Multilayer Interconnect
AHB Subsystem
AHB to APB Bus Bridge
APB Subsystem
AXI Multilayer Interconnect
AXI Subsystem
AXI to APB Bus Bridge

Other Peripherals
AXI4 to/from AXI4-Stream Scatter-Gather DMA
AHB/AXI/Wishbone DMA Controller
General-Purpose I/O Controller with APB Interface
Real-Time Clock with APB Interface
Smart Card Reader Controller
Timer/Counter with APB Interface
Watchdog Timer with APB Interface

Memory Controllers
AHB Cache Controller
Error Correcting Code for SRAMs
Static RAM Controller
xSPI Flash Memory Controller

Serial Communications
UART with Synchronous CPU Interface
UART with FIFOs and Synchronous CPU Interface
UART with FIFOs, IrDA and Synchronous CPU Interface
HDLC & SDLC Protocol Controller
I2C Master/Slave Controller
I2C & SMBus Controller
Octal SPI Master/Slave Controller
SPI to AHB-Lite Bridge

Encryption Primitives
Advanced Encryption Standard Engine
AES-CCM Authenticated Encrypt/Decrypt Engine
AES-GCM Authenticated Encrypt/Decrypt Engine
Programmable Advanced Encryption Standard Engine
AES-XTS Storage Encrypt/Decrypt Engine
AES Key Expander
Message Digest Algorithm Processor
256-bit SHA Secure Hash Crypto Engine
SHA-3 Secure Hash Crypto Engine

GEON Security
Secure Execution Processor
SoC Security Platform / Hardware Root of Trust

=== End of list

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=== Новости 2020 года от CAST:

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CAST Releases MIPI I3C Basic Slave Controller IP Core
New controller provides fast, low-power, royalty-free MIPI I3C interface for connecting sensors and peripherals to processors and includes I3C-to-AHB Bridge for quicker system integration

Woodcliff Lake, NJ—November 10, 2020

Silicon intellectual property provider CAST, Inc. today announced a new IP core that implements a slave controller for the MIPI®I3C Basic interconnection bus.

The new I3C-SMIPI I3C Basic Slave Controller core supports the latest I3C Basic specification, is suitable for any I3C bus topology,and is easy to configure and use. It includes—uniquely, the company believes—an I3C to AMBA AHB bridging mode. This enables an I3C bus master to access the on-chip AHB bus without additional software assistance, simplifying data exchange and remote monitoring and configuration.


Long-term CAST partner Silesia Devices developed the core. “We rolled twenty years of I2C customer experience into this competitive, user-centric IP core that delivers unmatched features and efficiency to developers using the new I3C Basic bus,” said Silesia Devices president Maciej Pyka. “The core also saves time and headaches with a built-in bridge between the I3C bus and the popular AMBA AHB bus, eliminating a step that system integrators previously had to do themselves.”

The new I3C-S MIPI I3C Basic Slave Controller core is available now for FPGA or ASIC designs. It is part of CAST’s broad IP product line, which also features compression engines, microcontrollers and processors, SoC security modules, and various other peripherals, interfaces, and IP cores.

Learn more by visiting www.cast-inc.com, emailing info@univeda.ru, or calling +7 985 9997272.

About MIPII3C and MIPI I3C Basic

MIPI I3C is a serial communication interface specification that improves upon the features, performance, and power use of I²C, while maintaining backward compatibility for most I2C devices. MIPI I3C Basic is technically identical to MIPI I3C, except with a reduced feature set and RAND-Z licensing. MIPI-I3C Basic was designed to be interoperable to MIPI I3C and intended to be royalty-free to all implementers in order to encourage fast and broad deployment of the new serial I3C serial bus. Learn more at the MIPI Alliance I3C page.

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CAST Releases 100Gbps UDP/IP Core
Woodcliff Lake, NJ — May 14, 2020

Lean networking protocol stack gets 512-bit datapath to increase communication speed, offloads UDP/IP functions from processor to improve system performance
CAST, Inc. today announced the availability of a new silicon intellectual property core enabling lean networking with the User Datagram Protocol (UDP) Internet Protocol (IP) at bidirectional speeds up to 100Gbps.

The UDP/IP protocol trades off the error resiliency of the common Transmission Control Protocol (TCP) for significantly faster networking with fewer hardware resources and less bandwidth consumption. This makes UDP/IP an excellent choice for applications where receiving most of the data packets on time matters more than receiving every single data packet—such as live video broadcasting—or for applications that employ other mechanisms for avoiding packet loss such as time-aware traffic shaping in Time-Sensitive Networking (TSN) networks or application-level data transport protocols like UDP-based Data Transfer (UDT).

UDPIP-100G UDP/IP Hardware Protocol Stack Block Diagram:

The new UDPIP-100G core includes a complete, full-featured UDP/IP hardware stack, with support for related networking standards and functions (such as ARP with cache, IGMP, and VLAN). It operates in stand-alone mode, offloading the demanding task of UDP/IP encapsulation/decapsulation from the system processor while transmitting and receiving data at speeds up to 100Gbps. Easy system integration—with industry-standard interfaces and pre-integration with popular Ethernet MAC cores—plus straightforward run-time configuration and numerous operating options help the UPDIP-100G core significantly reduce typical system design time.

CAST customers have reaped the benefits of UDP/IP since 2011, using these cores for data center acceleration, streaming or bulk data transfers in different types of communication systems and devices, real-time industrial control, and other applications. The well-proven IP and extensive application experience make the UDP/IP cores and support team from CAST one of the lowest-risk options available.

The UDP/IP-100G Hardware Protocol Stack core is available now, joining existing 1G and 40G UDP/IP Stacks in CAST’s Internet Protocol Stacks Family. These are part of the broad line of leading-edge and standards-based digital IP available from CAST, including compression engines; microcontrollers and processors; automotive interfaces; SoC security modules; and a variety of peripherals, interfaces, and other IP cores. Learn more by visiting www.cast-inc.com , emailing info@cast-inc.com, or calling +1 201.391.8300.

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Low-Latency Ethernet MAC IP Core from CAST now ASIL-D Certified
Automotive Ethernet Congress, Munich, Germany — February 11, 2020

ASIC and FPGA IP core is ready to reduce development time and risk for automotive system designers using Time Sensitive Networking (TSN) Ethernet

Semiconductor intellectual property (IP) provider CAST, Inc. today announced that the Low-Latency Ethernet Media Access Controller IP core it offers is now certified to conform to the ISO-26262 safety standard and is available ASIL-D ready.

LLEMAC-1G block diagram - here:

The LLEMAC-1G Low-Latency 10/100/1000 Ethernet MAC core features extremely low input and output latencies, making it ideal for TSN Ethernet nodes, live video streaming, and other systems requiring minimum delays in the reception and transmission of Ethernet frames. The company believes it is the first such low-latency EMAC ASIC and FPGA core to achieve ASIL-D safety certification, the highest degree of safety compliance under the ISO-26262 standard. This makes the LLEMAC-1G a smart choice for use with TSN Ethernet for the most life-critical automotive systems, including brakes, airbags, and power steering.

Sourced from partner Fraunhofer IPMS, the LLEMAC-1G core is compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications. It enables high-precision synchronization in TSN networks, with extremely competitive latencies of just six clock cycles for the reception and ten clock cycles for the transmission of packets. The Safety Enhanced version of the core includes an ISO-26262 “ASIL-D Ready” certificate, issued by SGS-TÜV Saar GmbH, as well as the Safety Manual (SAM) and Failure Modes, Effects and Diagnostics Analysis (FMEDA) needed for efficient ASIL-D implementation.

Automotive Ethernet Congress
Visitors to the 6th Automotive Ethernet Congress this week in Munich can discuss the new core with the Fraunhofer IPMS/CAST automotive networking team in booth 18C.

The LLEMAC-1G is available now, in synthesizable Verilog source code or as a targeted netlist for Intel, Xilinx, or Lattice FPGA devices. It joins TSN Switched Endpoint, TSN Endpoint, and CAN-to-TSN Gateway cores in CAST’s popular Automotive Interfaces family, which also includes IP for CAN 2.0/FD, LIN, and SENT. These are part of CAST’s broader IP portfolio, including 32- and 8-bit processors; hardware compression/decompression engines for data, images, and video; and numerous other interfaces and peripherals.

Learn more about CAST’s complete line of IP by visiting www.cast-inc.com, emailing info@cast-inc.com, or calling +1 202.891.8300.

CAST is a trademark of CAST, Inc. Other trademarks are the property of their respective owners. CAST, Inc., 50 Tice Blvd, Suite 340, Woodcliff Lake, NJ 07677 USA • phone: +1 201.391.8300

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CAST Adds Switched TSN Endpoint Controller to Time-Sensitive Networking Ethernet IP Cores Family
Woodcliff Lake, NJ — January 17, 2020

Enables easy implementation of small, low-power, low-latency TSN Ethernet nodes for daisy-chained or ring networks

Semiconductor intellectual property (IP) provider CAST, Inc. today announced the availability of a new IP core implementing a switched endpoint controller supporting the Time-Sensitive Networking (TSN) Ethernet standards.

The new TSN-SE TSN Ethernet Switched Endpoint Controller IP core integrates hardware stacks for timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav and IEEE 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.1Qbr), and a low-latency Ethernet MAC.

TSN Ring Network with CAST TSN-SE Switched Endpoint Controller Cores ( diagram based on the IEEE TSN Requirements Specification).

The company believes the TSN-SE to be one of the smallest and most energy-efficient such cores available, and it features remarkably low latency, implementing nearly every function in hardware. Furthermore, the endpoint controller portion of the core has been proven in multiple industry plugfests, public demos, and customer applications.

“Industrial and automotive systems designers can now build efficient TSN Ethernet ring networks with all the technical features, reliability, performance, easy reusability, and great customer support CAST IP cores are known for,” said CAST CEO Nikos Zervas.

About the TSN-SE Switched Endpoint Controller Core

Sourced from partner Fraunhofer IPMS, the new core builds on the Fraunhofer/CAST team’s market-leading technical and customer experience helping customers integrate TSN Ethernet and other industrial and automotive interfaces.

The highly-competitive core enables high-precision timing synchronization and flexible yet accurate traffic scheduling. Cut-through switching and minimal buffering—even at the Ethernet MAC level—enable extremely low and deterministic input and output latencies. Standard AMBA® interfaces and other features facilitate easy system integration, simplifying the development of time-aware daisy-chained networks.

The TSN-SE is available now, in synthesizable Verilog source code or as a targeted netlist for Intel, Xilinx, or Lattice FPGA devices. It joins TSN Endpoint and CAN-to-TSN Gateway cores in CAST’s popular Automotive Interfaces family, which also includes IP for CAN 2.0/FD, LIN, and SENT.

Block Diagram for CAST TSN-SE Time-Sensitive Ethernet Switched Endpoint Controller Core

These are part of CAST’s broader IP portfolio, including 32- and 8-bit processors; hardware compression/decompression engines for data, images, and video; and numerous other interfaces and peripherals.

Learn more about CAST’s complete line of IP by visiting www.cast-inc.com, emailing info@cast-inc.com, or calling +1 202.891.8300.

CAST is a trademark of CAST, Inc. Other trademarks are the property of their respective owners. CAST, Inc., 50 Tice Blvd, Suite 340, Woodcliff Lake, NJ 07677 USA • phone: +1 201.391.8300

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Megh Computing Uses CAST H.264 IP Subsystem in Video Analytics Solution
January 08, 2020 - 15:08

Low-latency Video Decoding IP Subsystem Meets Megh's Requirements for Video Analytics System Using AI/Deep Learning to Prevent Retail Inventory Loss

Megh Computing
Megh Computing, established in 2017, is based in Portland, OR with offices in Bangalore, India.

Megh Computing’s mission is to enable the 3rd wave of computing in data centers with the deployment of scale out FPGA (Field Programmable Gate Arrays) based accelerators.

The company’s solution provides a scalable, efficient platform for Real Time Analytics using FPGA-as-a-Service delivering high performance with low latencies for the edge, public or private cloud. For more information, visit www.megh.com.

The Challenge
Megh Computing had both a technical and business challenge. The technical challenge was very tight timing and performance specs.

As a start-up, the business challenge was to come up with a flexible licensing model that met both Megh Computing’s current and future economic requirements.

MEGH CEO - Prabhat Gupta
The Solution
Megh Computing uses the CAST Video Over IP subsystem that integrates a CAST H.264 decoder with the CAST RTP-to-H264 core for a low latency streaming solution.

This IP solution is used to decode video streams into image frames for segmentation and classification using deep learning on the streaming video. The application of this product is to use AI/Deep Learning to prevent retail inventory loss and to track inventory items in warehouses. Read Megh Computing’s blog on Using AI/Deep Learning to prevent inventory loss to get a more detailed description of their solution.

VAS System Requirements:

Megh Computing's Requirements for their video analytics pipeline.
What attracted Megh Computing to CAST was CAST’s technology and domain expertise, their support model and willingness to work with Megh Computing to meet Megh Computing’s stringent timing requirements and project schedule with CAST’s integrated H.264 subsystem. CAST worked with Megh Computing to provide a licensing model that met the needs of both a start-up and projected future growth. Megh Computing has recently demonstrated its Video Analytics Solution on the Intel Platform.

Key Challenges
Needed a partner with strong domain expertise.
Needed a partner who was willing to work with Megh Computing to meet their stringent timing requirements and project schedule.
Needed a flexible licensing model.
CAST Solutions
CAST’s integrated H.264 subsystem
CAST’s strong domain expertise and support.
Met and exceeded Megh Computing’s timing requirements and performance requirements.
CAST provided a flexible licensing model.

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Data Compression Accelerators from CAST Now Available on Xilinx Alveo Boards
Woodcliff Lake, NJ— September 27, 2019

Reduce bandwidth and storage requirements with standard GZIP/ZLIB/Deflate compression at over 90Gbps on Xilinx Alveo Data Center Accelerator Cards

Semiconductor intellectual property (IP) provider CAST, Inc. today announced that its GZIP/ZLIB/Deflate Compression and Decompression reference designs are now available on Xilinx®Alveo™ Data Center Accelerator Cards.

Already successfully deployed by multiple customers on Xilinx Kintex® and Virtex® Ultrascale FPGA boards, the GZIP-RD-XIL GZIP & GUNZIP Accelerator Reference Design now running on Xilinx Alveo PCIe cards delivers an unmatched combination of good compression ratio, low latency, and high throughout. As shown in Table 1, data compression at over 90 Gigabits per second (Gbps) is possible with the compression IP running on the mid-range Alveo U200 Card.

Full story here

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AES Encryption IP Cores from CAST Receive NIST Certification
Woodcliff Lake, NJ — October 24, 2019

Commercially proven AES encryption and decryption engines now certified to meet standard for function and interoperability

Semiconductor intellectual property (IP) provider CAST, Inc. today announced that its IP cores for AES encryption have received certification from the US National Institute of Standards and Technology (NIST) as being in compliance with NIST’s Federal Information Processing Standard (FIPS) Publication 197 and successive Special Publications.

Since 2001 when NIST first adopted it, AES, the Advanced Encryption Standard, has been the de facto standard for strong data protection. The FIPS conformance of CAST’s cores was tested by an independent laboratory, and the results reviewed and approved by NIST, which granted the AES certification.

Encryption NIST Graphic
“Our encryption cores are already proven in shipping products by several dozen customers, but this NIST certification provides an additional guarantee of reliability and interoperability make these AES cores even more competitive with the best available crypto engines,” said CAST CEO Nikos Zervas.

About the Certification
The AES cores are sourced from partner Ocean Logic (www.ocean-logic.com). They have been certified for the six main AES confidentiality encryption modes—Electronic Code Book (ECB), Cipher Block Chaining (CBC), Output Feedback (OFB), Cipher Feedback (CFB), Counter (CTR), and XTS-AES—and the primary AES combination modes—Counter with CBC-MAC (CCM) and Galois/Counter (GCM)—plus the Liskov-Rivest-Wagner (LRW) mode.

The AES cores were certified for all three possible encryption key sizes—128-bit, 192-bit, and 256-bit—except for the XTS-AES, which only supports 128- and 256-bit keys.

The 256-bit SHA cryptoprocessor (SHA-256) offered by CAST and sourced from Ocean Logic also successfully underwent NIST certification.

Review these NIST certification details at CAST’s Cryptographic Algorithm Validation Program entry.

About the IP Cores
CAST offers several fixed and programmable AES IP cores that produce hardware encryption and decryption engines with a range of features, performance, and silicon characteristics to suit a variety of applications. These and the SHA 256-bit Cryptoprocessor Core are part of the company’s Security IP family, which also includes other encryption primitives and the GEON Security Platform, a solution for complete system-on-chip (SoC) protection.

The Security cores are in turn part of CAST’s broader IP portfolio, including 32- and 8-bit processors; hardware compression/decompression engines for data, images, and video; and numerous interfaces and peripherals. Learn more about CAST’s complete line of IP by visiting www.cast-inc.com, emailing info@cast-inc.com, or calling +1 202.891.8300.

CAST is a trademark of CAST, Inc. Other trademarks are the property of their respective owners. CAST, Inc., 50 Tice Blvd, Suite 340, Woodcliff Lake, NJ 07677 USA • phone: +1 201.391.8300

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CAN to TSN Gateway from CAST Bridges CAN 2.0/FD Buses with Time Sensitive Ethernet
Woodcliff Lake, NJ — October 04, 2019

IP core provides easy integration of up to seven CAN buses with an Ethernet network in automotive and industrial systems; will be shown at TSN/A Conference

Semiconductor intellectual property (IP) provider CAST, Inc. today announced the availability of a CAN to TSN Ethernet IP core that gives automotive and industrial system designers an easy and cost-effective way to link CAN 2.0 and FD buses or devices with a Time Sensitive Ethernet network.

The company believes the CAN2TSN is among the first—and perhaps the only—available silicon IP solution for the growing challenge of integrating conventional and new networks in evolving, data-driven automotive and industrial systems. Developed by CAST using CAST IP and CAN and TSN cores sourced from partner Fraunhofer IPMS (www.ipms.fraunhofer.de), the new CAN-to-TSN Ethernet Gateway/Bridge provides:

CAN2TSN CAN-to-TSN Ethernet Gateway/Bridge Block Diagram:

Bridging of up to seven independent CAN 2.0 or CAN FD ports to a single TSN Ethernet port;
High-accuracy TSN timing synchronization (IEEE 802.1AS) of under 5µs and flexible TSN traffic shaping (IEEE 802.1Qav and IEEE 802.1Qbv);
Low-latency CAN to TSN routing of under 30µs for both directions;
Easy integration, with industry-standard interfaces to the system, Ethernet PHY, and CAN transceivers; and
Fast, efficient operation, with custom hardware stacks running most protocols.
The CAN2TSN Gateway IP core is shipping now. A complete CAN2TSN reference design board is also available; CAST will be demonstrating it with Fraunhofer IPMS in their booth at the TSN/A Conference in Bad Homburg, Germany, October 8–9, 2019.

The CAN2TSN CAN-to-TSN Ethernet Gateway/Bridge is part of CAST’s Automotive Interfaces IP suite, which also includes CAN, TSN, SENT, and LIN IP cores. Learn more about this and CAST’s complete line of IP by visiting www.cast-inc.com, emailing info@cast-inc.com, or calling +1 202.891.8300.

CAST is a trademark of CAST, Inc. Other trademarks are the property of their respective owners. CAST, Inc., 50 Tice Blvd, Suite 340, Woodcliff Lake, NJ 07677 USA • phone: +1 201.391.8300

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=== Новости 2018 года от CAST:

CAST Releases TSN Ethernet Subsystem for Automotive and Industrial Applications

TSN Reference Design also available was used in live demonstrations of Ethernet Time-Sensitive Networking at DAC


Semiconductor intellectual property provider CAST, Inc. concluded Design Automation Conference (DAC) week by announcing the only available IP subsystem implementing the latest IEEE standards for Time Sensitive Networking (TSN) over Ethernet.

TSN Ethernet has emerged as the preferred new bus for automotive and similarly challenging industrial applications. The new TSN_CTRL Ethernet Subsystem enables system designers to manage the ultra-low-latency communication and quality of service (QoS) attributes required for today’s increasingly sophisticated vehicles. It can, for example, ensure that a signal from obstacle avoidance sensors is given immediate processing with higher priority over competing signals from tire pressure sensors or the infotainment system, all without disturbing the critical network traffic related to engine or braking control.

The new TSN_CTRL Subsystem combines three essential IP cores to enable the high-precision timing synchronization and flexible yet accurate traffic scheduling needed to implement TSN Ethernet endpoints, bridges and switches:

a Time Synchronizer implements IEEE 802.1AS, automatically synchronizing the local time to the system’s (Grandmaster’s) time and generating timestamps and alerts needed for the development of time-aware nodes and applications;

a Traffic Shaper implements IEEE 802.1Qav and 802.1Qbv, providing bandwidth allocation and time multiplexing for up to eight traffic classes to ensure sufficiently low latency (delay) and minimum jitter as required; and

a specially-designed Ethernet MAC with ultra-low latency (delay) provides standards-based Ethernet functionality that works well with the Time Sensitive Networking.

The configurable TSN_CTRL IP implements a hardware subsystem that operates without software assistance once programmed. It communicates timing information to the system, and allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements.

The TSN_CTRL Subsystem uses standard AMBA®or Avalon®interfaces for straightforward system integration. Its configuration and status registers are accessible via a 32-bit-wide AXI4-Lite or Avalon-MM bus, and packet data are input and output via AXI-Streaming or Avalon ST interfaces with 8-bit data buses.

A complete TSN Reference Design is available for evaluation or to jumpstart system design. It implements a network bridge receiving three types of traffic:

a video stream captured from an HDMI port, compressed with the CAST H.264 low-latency encoder core and streamed over RTP and UDP,

a “sensor” signaling every 100msec, and

a programmable “other traffic” generator emulating other types of traffic on the backbone.

Without TSN traffic shaping, the three sources compete for bandwidth, resulting in packet loss, dropped video frames, and considerable sensor signal jitter. But with TSN traffic shaping, bandwidth can be reserved per traffic source, and specific time slots can be assigned for the delivery of each traffic source. This allows, for example, the video to be delivered at its full bit rate and hence without any frames loss, and the sensor signals to be delivered with minimum latency and no jitter.

The TSN_CTRL Ethernet Subsystem is sourced from Fraunhofer IPMS. It is available now, in synthesizable RTL or as a targeted FPGA netlist.

About CAST
In addition to the TSN Ethernet Subsystem and other leading automotive interface cores, CAST offers a range of compression solutions and image processing functions; 8051 microcontrollers and extreme-low-power 32-bit BA2X™ processors; and a variety of peripherals, interfaces, security, and other IP cores. CAST IP features easy integration and reuse, straightforward licensing, and availability for ASICs or FPGAs from all leading silicon providers. Learn more by visiting www.cast-inc.com, emailing info@cast-inc.com, or calling +1 201.391.8300.

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CAST Adds JPEG-LS Decoder to Lossless Image Compression IP Core Suite

CAST’s JPEG-LS Encoder and Decoder provide a scalable, zero-latency, ultra-low-power hardware solution for numerically- or visually-lossless image compression


Semiconductor intellectual property provider CAST, Inc. has released a JPEG-LS Decoder IP core that—together with the JPEG-LS Encoder already available—provides an efficient hardware compression solution for the lossless or near-lossless transmission or storage of high quality images or video sequences.

The JPEG-LS cores provide:

Superior compression ratios, yielding smaller files than PNG and smaller or similarly sized files than JPEG 2000 (see figure);

Ultra-low power consumption, thanks to the low complexity of the JPEG-LS algorithm, which enables hardware implementations with an extremely small silicon footprint and minimal memory requirements;

“Zero” (sub-millisecond) latency, because the line-based processing employed by JPEG-LS does not impose any buffering of frames or even image lines before the encoding or decoding process is initiated; and

Scalable throughput, uniquely handling ultra-high resolutions and/or frame rates by internally combining and managing a configurable number of parallel processing engines.

Chart: JPEG-LS yields better compression than PNG and similar or better than JPEG 2000.
Comparing the resulting file size and compression ratios of the PNG, JPEG 2000, and JPEG-LS lossless compression algorithms using typical images.

For example, consider the significant savings in hardware resources (16nm technology) possible for the lossless encoding and decoding of a 4K Ultra HD, 10-bit per color, RGB video stream at 30 frames per second:

JPEG 2000
several million gates
several Mbits of memory
more than 70mW
tens of msec of latency

350K gates
300 Kbits of SRAM
less than 10mW
less than 0.5 msec of latency

Moreover, the CAST JPEG-LS encoder will yield a similar or even better compression ratio as the JPEG 2000 encoder, resulting in further resource savings system-wide.

Their competitive compression ratio with smaller hardware and lower latency make the JPEG-LS Encoder and Decoder cores an excellent choice for systems where artificial intelligence or video analytics process the video stream—such as for autonomous driving or augmented reality applications—because these systems typically do not accept image quality loss or any extra latency, while also requiring very low power consumption. Additional applications include those requiring high quality images with maximum file size savings, including space and medical imaging (JPEG-LS is part of the DICOM medical imaging standard).

About the JPEG-LS IP Cores

The JPEG-LS-E Encoderand JPEG-LS-D Decodereach fully support the JPEG-LS, ISO/IEC 14495-1 standard, which is based on the LOCO-I (LOw COmplexity LOssless COmpression for Images) algorithm developed by HP. The JPEG-LS-E has been used in products where decoding has been performed with standard software JPEG-LS decoders. The CAST Decoder appears to be the only such JPEG-LS decompression core commercially available; it can be used with the JPEG-LS-E or any other standard-conforming JPEG-LS encoder.

The JPEG-LS cores are easy to integrate and use, employing standard AXI-Stream and APB interfaces and operating standalone without processor intervention once programmed. Each is available in two versions, size-optimized, and scalable-throughput.

The single-pipeline, size-optimized versions process a single sample per clock cycle and require just one image line of buffering. The Encoder and Decoder can each handle several hundreds of Msamples per second when mapped to an ASIC technology; require as few as 40,000 ASIC gates; and run up to about 600 MHz and 350 MHz, respectively (on TSMC 16nm with SVT cells).

The multiple-pipe, throughput-optimized versions internally aggregate a user-specified number of the single-pipeline cores, handling multiple samples each cycle to efficiently process images or video with ultra-high resolutions and/or very fast frame rates. This scalable throughput capability appears to be unique to the CAST JPEG-LS cores.

The silicon-validated JPEG-LS Encoder and Decoder are available now, with royalty-free licensing for either ASICs (RTL) or FPGAs (netlists) from popular silicon providers.

About CAST
In addition to the JPEG-LS cores, CAST offers a range of compression solutions and image processing functions; 8051 microcontrollers and extreme-low-power 32-bit BA2X™ processors; industry-leading automotive interfaces; and a variety of peripherals, interfaces, security, and other IP cores. CAST IP features easy integration and reuse, royalty-free licensing, and availability for ASICs or FPGAs from all leading silicon providers. Learn more by visiting www.cast-inc.com, emailing info@cast-inc.com, or calling +1 201.391.8300.

# # #

Resurgence in 8051 Microcontroller Applications Drives New IP Cores Sales for CAST


Semiconductor intellectual property provider CAST, Inc. has seen a significant upswing in licenses for the venerable 8051 microcontroller, as today’s designers rediscover that the simplicity, low-power operation, small silicon area, and relatively inexpensive cost of this 8-bit MCU are an excellent match for the demands of many modern products. Specifically, in just the first quarter of 2018, CAST 8051 licenses were up by 30% compared to all of 2017, and reached their highest level for the last twelve years.

cast 8051 product iconCAST first introduced 8051 IP cores in 1997, marked its 200th license in 2013, and has continued healthy sales since then. Early applications ranged “from washing machines to space probes,” and today 8051s from CAST have been in hundreds of thousands of shipped customer products.

Continuous improvements over twenty years led to performance many times greater than envisioned by the 8051’s architects, while retaining compatibility with the original MCS-51 instruction set architecture. Silicon area and memory requirements have shrunk with IP maturity, and improvements to configurability, deliverables, and packaging have simplified 8051 development, integration, and testing. There is also a full ecosystem of evaluation options, programming tools, debugging hardware, reference design boards, and more, making the 8051s available from CAST some of the easiest MCUs to use.

Today these benefits make modern 8051 IP cores an excellent solution for Internet of Things and other applications with constrained power availability. One CAST customers’ wireless communications SoC, for example, operates strictly by harvesting the energy it needs from the environment. Designers today also value the reliability of the 8051 and use it in automotive, industrial, and space applications. New designs use 8051s in a variety of roles such as a power-management controller; the control and calibration engine for sensors, analog front ends, and high-speed serial interfaces; or the processor executing low-level software stacks for wireless and other communication protocols. Beyond the technical advantages, CAST’s royalty-free licensing makes its 8051s especially attractive for high volume applications.

“8051 compatibles have been a mainstay of the CAST IP product line for two decades,” said Nikos Zervas, chief executive officer for CAST. “We had thought 32-bit processors like our BA2X line would eventually replace the 8051s, but we’re excited to continue providing—and improving—these 8-bit wonders for designers who find them a great solution for a whole new set of system design challenges.”

About the 8051-Compatible MCU Family
The 8051-Compatible Microcontroller IP Cores Family available from CAST is a cost-effective range of MCS-51 conforming 8- and 16-bit microcontrollers with a variety of options for performance, size, peripherals, and configurability. It includes some of the fastest and the smallest such cores available, plus integrated hardware debugging options, reference designs and hardware/software evaluation boards, and support by leading software development environments,

The 8051 MCU IP cores are sourced from Silesia Devices, whose engineers created some of the first such cores ever developed and are today world-leading experts in MCS-51 microcontrollers and related systems. Learn more at www.silesia-devices.com.

About CAST
In addition to the 8051 family, CAST offers extreme-low-power 32-bit BA2X™ processors; industry-leading automotive interfaces and data compression solutions; a range of video and image processing functions; and a variety of peripherals, interfaces, security, and other IP cores. CAST IP features easy integration and reuse, royalty-free licensing, and availability for ASICs (RTL) or FPGAs (netlists) from all leading silicon providers. Learn more by visiting www.cast-inc.com, emailing info@cast-inc.com, or calling +1 201.391.8300.

# # #

CAST and Achronix Enable Processing from Data Center to the Edge with Lossless Compression IP

CAST Compression IP Integrated with Achronix eFPGA Technology for High-Performance, Low-Power Solution to Move and Store Big Data

Santa Clara, Calif., April 10 2018

Achronix Semiconductor Corporation, a leader in field programmable gate array (FPGA)-based hardware accelerator devices and embedded FPGA (eFPGA), announced its collaboration withCAST Incorporated, a semiconductor intellectual property company focusing on semiconductor IP for electronic system designers. CAST’s high performance lossless compression IP has been ported to support the Achronix portfolio of FPGA products, enabling efficient processing for Data Center and Mobile Edge Data transfer.

CAST offers a hardware implementation of the lossless compression standard for Deflate, GZIP, and ZLIB that is compatible with software implementations used for compression or decompression. The hardware implementation provided by the ZipAccel core provides high throughput – up to 100Gbps – with very high compression performance and low-latency. Coupling this with Achronix Speedcore eFPGA technology enables a high-performance, low-power solution facilitating moving and storing big data.

With the explosion of applications employing analytics, the need to transfer increasing amounts of information through bandwidth limited communication channels is found from automotive systems to large financial institutions. The cost and power to transport data is becoming significant and compression implemented with Achronix eFPGA can minimize power and maximize the capability of the network. The combination of CAST compression IP and Speedcore eFPGA IP on a custom SoC effectively increases the achievable throughput; in addition developers can utilize the eFPGA to rapidly and efficiently implement data processing algorithms.

The ability to optimize the compression algorithm in the eFPGA to address a system’s specific throughput, storage and latency requirements makes this solution a consideration for hundreds of applications. Not only can throughput be increased, but significant savings in expensive memory storage can be realized.
“We are pleased to be working with CAST as part of the Achronix Partner Program,” says Mike Fitton, Achronix senior director, product planning and business development. “The ability to instantiate CAST’s high throughput compression cores in our eFPGA allows Speedcore-enabled ASIC and SoCs to efficiently address the data server market. The availability of eFPGA IP as a workload-specific, reprogrammable hardware accelerator enables new algorithms, including compression but also data analytics, to be rapidly implemented. The high performance of Speedcore eFPGA, coupled with its significant market traction makes it ideal for this application.”

“CAST is happy to license the core to Achronix customers who benefit from Achronix’s unique architecture which provides rapid flexibility, future-proofing and time-to-market for new algorithms” remarks Nikos D. Zervas, CEO of CAST Inc. “Having a proven IP solution for the Achronix FPGA toolchain and architecture facilitates the design time of our customers who have requested implementation in Achronix FPGAs and eFPGA. The IP is further optimized to take advantage of the Achronix FPGA architecture for speed and reduced size.”

About ZipAccel

ZipAccel-C’s flexible architecture enables fine-tuning of its compression efficiency, throughput, area and latency to match the requirements of the end application. CAST engineers provide data and analysis to help in determining trade-offs between various configurations of the core and provide support of evaluations with customer specific data samples.

About Speedcore eFPGA

Speedcore eFPGA IP can be integrated into an ASIC or SoC to provide a customized programmable fabric. Users specify their logic, memory and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements. Speedcore look-up-tables (LUTs), RAM blocks and DSP64 blocks can be assembled like building blocks to create the optimal programmable fabric for any given application.

About CAST Inc

CAST develops, aggregates, and integrates digital IP cores and subsystems. The company’s product line includes low-power, high-value, processors, video and image codecs, peripherals, interfaces, and more; see details at www.cast-inc.com.

About Achronix Semiconductor Corporation

Achronixis a privately held, fabless semiconductor corporation based in Santa Clara, California. The company developed its FPGA technology which is the basis of the Speedster22i FPGAs and Speedcore eFPGA technology. All Achronix FPGA products are supported by its ACE design tools that include integrated support for Synopsys (NASDAQ:SNPS) Synplify Pro. The company has sales offices and representatives in the United States, Europe, and China, and has a research and design office in Bangalore, India.

# # #

CAST and Accelize Make GZIP Compression Instantly Available via Cloud-Based FPGA Accelerators

Hardware Accelerated GZIP Data Compression Available on As-Needed Basis in New AccelStore

WOODCLIFF LAKE, NJ USA — April 9, 2018 — Semiconductor intellectual property provider CAST, Inc. has taken advantage of a new cloud-based FPGA accelerator marketplace developed by Accelize® to make industry-leading GZIP data compression available to users and developers whenever they need it.

The new AccelStore™ makes critical functions like GZIP directly available to end users on a rental by time or data basis. The cloud-based IP functions run on optimized FPGA accelerator boards hosted in high-speed data centers including those of Amazon Web Services (AWS) and OVH. Accelize gives IP developers technical tools and support and manages the licensing and cloud hosting; its AccelStore then makes the online library of accelerated functions available with easy licensing and usage.

“Accelize has made the promise of hardware-agnostic cloud-based accelerators really work,” said Nikos Zervas, chief executive officer for CAST. “We still of course offer reusable GZIP IP cores to conventional system and product developers, but now AccelStore gives CAST a new revenue stream by making accelerated GZIP compression easy to deploy and affordable to use on cloud servers.”

"CAST has been a longtime partner of Accelize and an early believer in the value of bringing powerful FPGA based Accelerator Functions to cloud users," said Stephane Monboisset, vice president of marketing and partnerships for Accelize. "Their GZIP compression IP and associated Accelerator Function are of high quality, and our tight partnership enables us to tune these functions to the exact needs of cloud users to provide maximum value for most compression needs."

About Accelize

FPGA hardware accelerators have been getting significant attention for the speed and processing power they offer for compute-intensive functions. Where Accelize has succeeded is in making FPGA acceleration practical and affordable for the scientists, statisticians, researchers, and other end users who need it most. They’ve done this by assembling an ecosystem that unites IP developers like CAST, FPGA accelerator silicon providers like Intel® and Xilinx®, and hosting companies like AWS and OVH, to deliver cloud-based accelerated functions. Enterprise versions of the AccelStore are also available so companies can provide FPGA acceleration to their employees.

Potential FPGA accelerator users should visit the AccelStore to see the available functions. IP and other developers interested in participating should visit www.accelize.com to learn more.

About the GZIP IP & CAST

The ZipAccel™-C GZIP/ZLIB/Deflate Data Compression IP Core provides extremely fast lossless data compression with relatively high compression ratios. Throughputs in excess of 100 Gbps are feasible even in low-cost FPGAs, and latency can be as small as a few tens of clock cycles. A similarly beneficial Decompression core is also available. The GZIP cores are part of the broad line of digital IP cores and subsystems offered by CAST. Learn more about CAST’s line of processors, video and image processing, peripherals, interfaces, and security cores by visitingwww.cast-inc.com, emailing info@cast-inc.com, or calling +1 201.391.8300.

Accelize is a registered trademark and AccelStore a trademark of PLDA Group. CAST is a trademark of CAST, Inc. Other trademarks are the property of their respective owners.

# # #

=== Новости 2017 года от CAST:

Novatek Reduces TV Boot Time with Data Decompression IP Core from CAST

Novatek Microelectronics Corp., a customer of semiconductor IP provider CAST, Inc., has applied a data decompression IP core to achieve a major consumer benefit: significantly reduced start-up delay in digital televisions.

Consumers don’t like to wait when they turn on a television set. Much of this start-up or “boot time” delay is due to the time required to read the initial firmware code out of the relatively slow, non-volatile, flash memory where it is stored. Novatek’s innovation dramatically reduces this boot time by storing a much smaller, compressed version of the firmware, and using a fast hardware decompression engine obtained from CAST to rapidly decompress the code during boot.

Novatek Logo & CAST IP purchase news
The ZipAccel-D GUNZIP/ZLIB/Inflate Data Decompression IP Core available from CAST is a hardware decompression engine with remarkably low latency and high throughput. Novatek successfully used its initial single-use license for the core in one of its highly integrated, programmable, system-on-chip (SoC) products targeted to digital TV manufactuers, then upgraded to a multi-use license to apply the technology to additional chipset products. The approach not only increases consumer satisfaction with a shorter boot time, but also reduces system costs by enabling the use of smaller, less expensive memory devices.

GZIP IP product icon
“The GUNZIP core from CAST was relatively easy to integrate, functions and performs well, and gives our DTV chipsets a distinct competitive advantage,” said Daniel Ping, television products director for Novatek. “The core itself is well-designed and packaged, and CAST’s excellent technical service and support has helped us meet or exceed our project schedules.”

The decompression engine Novatek licensed is part of the ZipAccel™ family of data compression IP CAST sources from Sandgate Technologies. A compression engine and complete PCIe Compression Reference Design Kit are also available. Other CAST customers have used ZipAccel engines to reduce boot time and energy consumption in a variety of application areas; read about this approach in the CAST white paper Firmware Compression for Lower Energy and Faster Boot in IoT Devices.

About Novatek
Novatek Microelectronics Corp. is a Taiwanese fabless semiconductor company established in 1997 and specializing in display-centered total solutions in a line of ICs and SoCs for all display applications. The company is the world’s largest supplier of display driver ICs, and is ranked as the world’s 10th largest and Taiwan’s 2nd largest fabless company in terms of sales revenue (2015). With successful sales to major TV OEMs around the world, Novatek has been identified as one of the firms dominating the rapidly-growing Ultra HD chipset market (Strategy Analytics research report).

For more information, visit www.novatek.com.tw.

About CAST, Inc.
CAST develops, aggregates, and integrates digital IP cores and subsystems. The company’s product line includes low-power, high-value, processors, video and image codecs, peripherals, interfaces, and more; see details at www.cast-inc.com.
# # #

CAST Introduces GZIP Accelerator Through New Intel FPGA Data Center Acceleration Ecosystem
WOODCLIFF LAKE, NJ USA, October 17 2017

A hardware accelerator that addresses the data compression and storage optimization needs of performance-critical data center applications is now available from semiconductor intellectual property provider CAST, Inc. This GZIP Accelerator Function is part of the expanded Intel® FPGA Design Solutions Network (DSN), of which CAST is an early member.

The CAST GZIP Accelerator integrates the popular ZipAccel-C™ GZIP/ZLIB/Deflate Compression IP Core with a PCIe interface, Direct Memory Access (DMA) function, and essential driver software in a high-performance, plug-and-play FPGA data compression system. Lossless data compression rates can exceed 40 Gbps, making the GZIP Accelerator an excellent choice for servers or database applications, where its data compression optimizes storage requirements or reduces network bandwidth needs.

GZIP-RD-A10 Block Diagram and Board

The CAST GZIP Accelerator (GZIP-RD-A10) IP implemented in an FPGA on the
Intel Programmable Acceleration Card (PAC).

The CAST GZIP Accelerator is now available as a ‘drop-in’ accelerator function for the Intel Programmable Acceleration Card (Intel PAC) with Intel Arria 10 GX FPGA that is then added to servers. The Intel PAC card also pulls in frameworks and libraries using the Intel Acceleration Stack for Intel Xeon CPU with FPGAs, easing the use of FPGA acceleration.

“We’re seeing strong demand for our hardware GZIP data compression solution from data centers and other data-heavy or performance-critical applications,” said Nikos Zervas, chief executive officer for CAST. “Running this industry-leading GZIP accelerator on the Intel PAC with the Intel Acceleration Stack provides a significant win for customers needing faster data compression and decompression.”

“Intel is collaborating with a growing ecosystem of partners in our DSN program to bring new data center accelerator functions such as CAST’s GZIP data compression to our customers seeking options to accelerate workloads,” said Reynette Au, vice president of marketing, Intel Programmable Solutions Group. “Customers and end users can benefit with faster time to market by using IP from CAST and the larger ecosystem built around our Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA.”

The CAST GZIP Accelerator is available now from CAST (www.cast-inc.com). Learn more about the accelerator function or the Intel FPGA DSN program at www.altera.com/dsn.
# # #

CAST Drives Automotive IP Forward with New AVB/TSN Ethernet and SAE J2716 Sensor Bus Cores plus CAN-FD Time-Stamping
New IEEE 802.1AS AVB/TSN and SENT/SAE J2716 Cores now available; CAN/CAN-FD Controller Core now supports AUTOSAR-compliant time-stamping


Automotive IP
Semiconductor intellectual property provider CAST, Inc. today announced three significant improvements to its automotive IP family:

A new IEEE 802.1AS Hardware Protocol Stack Core works with any eMAC (Ethernet Media Access Controller) to enable easy development of time-aware nodes for standard AVB/TSN (Audio Video Bridging/Time Sensitive Networking) networks. This serves a variety of audio/visual and industrial applications, and is essential for the growing use of Ethernet to connect diverse automotive systems.
A new, full-featured SENT/SAE J2716 Controller Core serves as a transmitter and/or receiver for the Single Edge Nibble Transmission protocol. It complies with the SAE J2716 standard and also the de-facto standard Short PWM Code (SPC) protocol, and can serve as a simpler, lower-cost alternative to the popular LIN bus for connections between automotive sensors and controllers.
The CAN 2.0 & CAN FD Bus Controller Core now supports time-stamping compliant to the CiA 603 specification, which enables efficient hardware time-based synchronization for AUTOSAR (AUTomotive Open System ARchitecture) systems. This adds time-sensitive application support to one of the most field-proven, feature-rich, and transceiver-agnostic FPGA/ASIC CAN controller cores on the market. [A1]
“Working with multiple CAN FD customers every month has made us acutely aware of the special needs of automotive system designers,” said Nikos Zervas, chief executive officer for CAST. “These engineers face a growing demand for more sophisticated electronics at all levels in the market, and we believe these additions to our automotive IP line will further help them succeed in the face of rising complexity and diminishing time to market and cost flexibility.”

The CAN Controller and 802.1AS Stack cores are sourced from Fraunhofer IPMS. The SENT/J2716 Controller core was developed by CAST’s USA engineering team. All are available now, with royalty-free licensing.
# # #

CAST Adds DO-254 Avionics Interface Cores though New Partnership with Nolam
Nolam IP cores for MIL-STD 1553, ARINC-429, and ARINC-825 are field-proven and DO-254 compliant

Woodcliff Lake, NJ, June 01 2017

Semiconductor IP provider CAST, Inc. today announced a new partnership with Nolam Embedded Systems, and the resulting availability through CAST of several Nolam avionics-related IP cores.

Logo for CAST Avionics IP partner Nolam Embedded SystemsNolam Embedded Systems is a successful developer and integrator of real-time embedded systems. The company provides IP, board-level, and complete integrated system products, and primarily serves the aerospace, defense naval and aerospace, and industrial markets.

The partnership initially focuses on adding three Nolam IP cores for avionics standards to the CAST product line:

The MIL-STD 1553 core is a serial data bus controller for avionics, space, and server environment applications. It supports single, dual or quad channels and the standard’s BC, RT, and BM modes.
The ARINC-429 core is a point-to-point serial data bus controller typically used in commercial aircraft systems. It supports any number of receiver and transmitter channels.
The ARINC-825 core is a bus controller conforming to this aerospace-tailored version of the CAN 2.0 bus standard.
DO-254 design process compliance is available for all three cores—with Certification Data Packages for Design Assurance Levels E through A—eliminating for developers of safety-critical products the difficult challenge of satisfying this quality standard. Furthermore, these cores have already been deployed in numerous customer designs, proving their reliability and robustness in the field. A complete supporting ecosystem is readily available, including FPGA mezzanine cards (FMCs) for easy evaluation prior to purchase.

Do-254 compliant Avionics IP from CAST, Inc.“Lives are literally at stake if the buses and interfaces deep within airplane systems ever fail to perform,” said Nikos Zervas, chief executive officer for CAST. “System designers aware of our leadership in CAN FD have often asked for DO-254 qualified avionics cores, and we’re very happy now to not only satisfy their requests but to actually surpass their expectations with these robust and field-proven cores from Nolam.”

“At Nolam Embedded Systems, we’ve built our reputation on developing the appropriate technical solutions for the challenging markets we serve,” said Benjamin Nakache, vice president of sales for Nolam. “We’re now proud to partner with CAST—one of the world’s best in their field of marketing and selling IP cores—to help get Nolam IP to even more design teams who might benefit from it.”

The new cores have undergone CAST’s quality and reusability reviews, and are available this month with CAST’s royalty-free licensing. Each is ready for FPGA implementation and is vendor and device agnostic. Visit www.cast-inc.com to see technical data, request evaluation systems, and more.

About Nolam Embedded Systems
Founded in 2006, Nolam has developed innovative, board-level products and systems that help it lead the aerospace, defense, naval, medical, telecom, and industrial markets. Nolam’s in-house engineering team helps customers define project specifications and develops solutions from drivers and system software through IP cores to FPGA hardware systems, complete with all artifacts necessary for DO-264 up to DAL-A compliance packages. Customers include EADS (Airbus Group), Israel Aerospace Industries, Kongsberg Defence Systems, MBDA Missile Systems, and Thales.

Visit www.nolam.com to learn more about Nolam Embedded Systems.

About CAST, Inc.
CAST develops, aggregates, and integrates digital IP cores and subsystems. The company’s product line includes low-power, high-value, processors, video and image codecs, peripherals, interfaces, and more; see details at www.cast-inc.com.
# # #

=== Новости 2016 года от CAST:

CAN FD Bus Controller IP Core Gains Time-Triggered TTCAN Capability.
Available from CAST, Inc. this fully-featured soft CAN FD core supports all relevant specs, has Verification IP available, and will undergo its second Plug Fest in April

Nuremberg — Embedded World, February 23 2016

Semiconductor intellectual property provider CAST, Inc. today introduced standard support for the new Time-Triggered communication on CAN (TTCAN) protocol in the CAN Bus Controller IO Core it offers.

This CAN-CTRL CAN 2.0 & FD Controller Core, sourced from partner Fraunhofer IPMS, is among the few ASIC RTL and FPGA netlist cores to support TTCAN, the Flexible Data-Rate CAN FD protocol, and all popular CAN bus specifications:

CAN 2.0 and CAN FD — ISO 11898-1:2015 and earlier ISO, and Non-ISO (Bosch) versions
TTCAN — Time-Triggered CAN (ISO 11898-4 level 1)
Optimized support for the AUTOSAR and SAE J1930 specifications.
This CAN core was the first soft core to undergo rigorous testing at the CAN Open Plug Fest (in March 2015), and is scheduled for a second round at Detroit and Nuremberg Plug Fests in April and June respectively. Subsystem boards with the CAN-CTRL core and transceivers from ON Semiconductor and Microchip will be used in these strenuous evaluations.

Design verification for CAN-CTRL Core customers is facilitated through a partnership with verification IP expert Avery Design Systems. Developed independently but cooperatively, the Avery CAN 2.0 and FD VIP works “out of the box” with the core to provide smooth design and verification.

A ready-to-run reference design board and other development aids are also available from CAST to further shorten the time to market for CAN FD based systems. Visitors to Embedded World and DVCon (San Jose) are welcome to stop by the CAST booth for more information.

CAST, Inc. is a twenty-year-old developer, integrator, and aggregator of IP cores for ASICs and FPGAs. The company offers some of the best available choices for low-power, high-value IP, including 8051s and BA2x 32-bit Processors; video, image, and data compression; peripherals, interconnects and other functions needed for complete system designs. Visit www.cast-inc.com, or follow @castcores on Twitter.
# # #

New Tiny 80251 Beats Other Low-Power, High-Capability Microcontroller Options.
Available from CAST, Inc. this fast, easy-to-program, peripherals-loaded 16- and 32-bit controller needs less silicon area and code memory space and fewer memory operations than most 8-bit 8051s or 32-bit RISC processors

Nuremberg — Embedded World, February 23 2016

Semiconductor intellectual property provider CAST, Inc. today introduced a new microcontroller in its 8051-compatible IP line, the T80251XC3 Tiny, Configurable, 16-bit 80251 Microcontroller IP Core.

The new MCU is optimized to provide the 16- and 32-bit data processing capabilities of the 80251 architecture in less than 13K gates, a silicon area no larger than a fast 8-bit 8051 and much smaller than a typical 32-bit processor. It further offers system-wide cost and energy savings through greater code density for 16-bit processing—enabling the use of smaller firmware memory units—and a CISC design using more complex addressing modes that slashes the number of power-consuming load-store operations typically comprising 20–25% of the code for 32-bit RISC designs.

In addition to smaller size and less cost, the Tiny 80251 offers advantages that make it an excellent match for many modern applications. Sourced from partner Silesia Devices—one of the most experienced 8051 IP development teams in the world—the design is carefully optimized for performance and achieves a Dhrystone benchmark score of 0.1455 DMIPS/MHz (using the Keil compiler). A fully configurable set of proven peripherals is included and the 8051 ecosystem is mature, simplifying and reducing the risk of developing systems using the T80251XC3. Finally, the royalty-free licensing fees for the Tiny 80251 are likely much lower than for other advanced MCUs, further enabling low product pricing in IoT and similarly competitive markets.

Visitors to Embedded World and DVCon (San Jose) are welcome to stop by the CAST booth for more information.

CAST, Inc. is a twenty-year-old developer, integrator, and aggregator of IP cores for ASICs and FPGAs. The company offers some of the best available choices for low-power, high-value IP, including 8051s and BA2x 32-bit Processors; video, image, and data compression; peripherals, interconnects and other functions needed for complete system designs. Visit www.cast-inc.com, or follow @castcores on Twitter.
# # #

=== Новости 2015 года от CAST:

CAST and Boost Valley Partner for Better Verification of IP Cores
ссылка здесь.

CAST Makes Evaluating 32-bit Processor IP Easier with Talos for BA20 Plus FreeRTOS
ссылка здесь.

New 80251 Microcontroller IP Core Available from CAST is the World’s Fastest 8051-Compatible
ссылка здесь

CAST Introduces Secure GZIP/Deflate Data Compression IP Cores from Sandgate Technologies
ссылка здесь

MIPI® Support Added to Multilayer LCD Display Controller Available from CAST
ссылка здесь

CAST 8051 IP Line Expands with IAR Systems Tool Support and New Tiny 8-bit MCU
ссылка здесь

=== Новости 2014 года от CAST:

First CAN FD Bus Controller IP Core for ASICs & FPGAs Available Now from CAST

Woodcliff Lake, NJ — January 22, 2014 — Semiconductor intellectual property provider
CAST, Inc. is now shipping what it believes is the first available CAN Bus Controller soft IP
core that supports the recent CAN Flexible Data specification.

Sourced from Fraunhofer IPMS, the revised product adds FD support to the CAN 2.0
controller core CAST has carried for several years. The core’s FD extension completely
supports the CAN with Flexible Data-Rate Specification released by Bosch in April 2012.

This improved data link layer protocol significantly increases bandwidth, making the CAN bus
suitable for the greater demands of modern automotive, industrial control, and other systems.
As provisioned by the spec, the new core imposes no changes on the physical layer, allowing
the gradual updating of existing CAN networks with CAN FD capacities.

“CAN FD makes the stability and reliability benefits of the CAN bus available to designers of
today’s more data-hungry systems, and we’re excited to be the first delivering this capability
in an easy to use and integrate soft core via our partnership with Fraunhofer,” said Nikos
Zervas, chief operating officer for CAST. “The flexibility and performance of this royalty-free
CAN controller core have already helped some fifty customers get to market on time and on
budget, and we expect this FD option to help many more.”

The CAN Controller 2.0/FD IP core is available in VHDL or Verilog source code, or FPGA
netlists. Deliverables include scripts and a testbench for basic verification; work is underway
with Avery Design Systems for a complete suite of CAN FD-compatible Verification IP.

CAST, Inc. is a 20-year-old developer, integrator, and aggregator of IP cores and
subsystems. The company’s royalty-free product line features 8- and 32-bit controllers and
processors with peripherals; video and image compression codecs; and graphics, encryption,
interconnect, and interface IP for quickly building complete systems. See www.cast-inc.com
for product details.
# # #

=== Новости 2013 года от CAST:

CAST Introduces H.264 Video Over IP Subsystem to Simplify Video Streaming Product Development

Woodcliff Lake, NJ — October 11, 2013 — Semiconductor intellectual property provider CAST, Inc. has released a reusable subsystem and suite of hardware reference designs that make it easier to build video streaming into mobile and other products.

The new H264OIP-HDE Subsystem integrates three IP cores available from CAST: the H.264 High Profile Video Encoder (H264-HP-E) core for high-quality video compression, and the RTP and UDP/IP hardware stacks for encapsulating video for Internet Protocol transmission. Flexible video, memory, and network interfaces simplify system integration, and optional logic blocks enable standalone, processor-free subsystem operation. Available hardware reference design systems provide a turnkey jumpstart to streaming system development.

The new subsystem is an especially competitive solution for low-latency applications that demand minimal video delay. The advanced rate control capabilities of the H.264 encoder core, the near-zero latency of the hardware RTP/UDPIP encapsulation, and the ability to directly process the uncompressed video stream as presented by the capturing device together enable the H264OIP-HDE Subsystem to stream video with ultra-low—sub-5ns—latency. Furthermore, the subsystem’s dedicated hardware implementation means it consumes significantly less energy than any similar software-based alternative.

“This new video over IP subsystem makes the superior H.264 compression we offer drop-in ready for high-performance, low-latency, low-energy, video streaming over Ethernet or Wi-Fi,” said Nikos Zervas, chief operating officer for CAST. “Completing the solution are FPGA reference designs for turnkey HDMI- or DVI-to-Ethernet streaming in hardware, and customization services through which we can deliver a pre-packaged and fully-verified combination of any video-in or network controllers a customer requires.”

Reference designs for the streaming subsystem are available now for the Altera® Stratix® IV and Arria® V families, and the Xilinx® Kintex®-7 line. These include the CAST and other essential IP cores implemented in an FPGA, plus the necessary interfaces, memory, drivers, and software.

CAST’s IP customization services are available to integrate the Subsystem with a variety of memory controllers, input video interfaces (e.g., DVI, HDMI, MIPI-CSI, or SDI), and IP-based MAC controllers (e.g., Ethernet or 802.11 Wi-Fi). Other options include multiple video channels, different video preprocessing modules, or different compression algorithms (e.g., JPEG or JPEG 2000), and mapping the subsystem to different FPGA platforms.
The H264OIP-HDE Subsystem in RTL for ASICs or netlists for FPGAs is available now, including the H.264 Encoder Core (sourced from Alma Technologies SA) and the CAST RTP and UDP/IP Cores, other essential functions, complete documentation, and more. Call CAST at +1 201.391.8300 or visit www.cast-inc.com for more information.
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Low-Power BA21 Processor Core Brings 32-bit Benefits to Embedded Microcontroller Applications

Design Automation Conference — Austin, Texas, USA — June 3, 2013 — Processor intellectual property company Beyond Semiconductor and IP provider CAST, Inc. today unveiled the ultra-low power BA21™ embedded processor, further expanding the BA2x™ family of 32-bit processor cores.

The BA21 Low-Power Embedded Processor delivers 32-bit processing capability in a small, energy-efficient package, achieving 2.5 CoreMarks, operating up to 125 MHz, and needing under 10K gates (with a 65nm process). Its two-stage pipelined design is optimized for low power consumption in deeply embedded applications such as wireless communications or mixed-signal control. It offers a powerful step up from 8-bit microcontrollers used for such applications, as well as being a more efficient choice over larger general-purpose system processors.

“The world’s rush towards big data accessed anywhere requires devices that can capture, process, and analyze information within severe power budgets, and this can only be achieved through highly efficient hardware designs,” said Matjaž Breskvar, chief executive officer of Beyond Semiconductor. “To address such needs, this new BA21 core applies unmatched design efficiency to the most area- and power-sensitive end of the processor spectrum, doing more work in less silicon and using less energy than any comparable 8-, 16-, or 32-bit processor. It’s the perfect fit for the next generation of intelligent sensors, deeply embedded devices, or as a helper in complex SoCs.”

Energy consumption levels for a BA21-based system can be as low or lower than those possible with any competing processor thanks to the small silicon footprint, extreme code density, and lower memory demand of the BA2™ instruction set architecture (ISA). Effective power management functions such as clock gating of unused units and hardware or software controller dynamic frequency scaling further reduce energy usage. Options for expanded capabilities include floating point functions, hardware multiplication/divide, vectored interrupt control for fast response, and a memory protection unit.

“The royalty-free BA2x family has a growing reputation for offering a smart, technically-competitive IP choice in a processor market dominated by a single provider,” said Nikos Zervas, vice president for marketing of CAST. “CAST has long been a leader in 8051 applications and for last few years our customers have been asking for greater capabilities for more advanced designs. The BA21 is the perfect answer to that request: it offers great appeal to designers seeking to differentiate their products through better performance, lower energy usage, quick development, and a lower price point.”

The BA21 comes bundled with a customizable set of peripherals and functions. It expands the BA2x Family of 32-bit processors, complementing the mid-range BA22™ and the higher-end BA25™ full application processor. All support the BA2 instruction set architecture, which provides efficient operation and extreme code density for greater system-wide power savings.

Product packages include the Eclipse- and GNU-based BeyondStudio™ tool set to facilitate software development. A complete BA21 system board is available for easy evaluation or as a quick software development platform.

Already in use by early customers, the BA21 Low-Power Embedded Processor Core is available immediately, and will be highlighted in CAST’s booth at DAC (#2024).

BA2x, BA21, BA22, BA25, and BeyondStudio are trademarks of Beyond Semiconductor. All other trademarks are the property of their respective owners.
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Ultra-Low Latency H.264 Video Encoding Now Available from CAST

Woodcliff Lake, NJ — May 16, 2013 — The H.264 video encoder IP cores available from semiconductor intellectual property provider CAST, Inc. now feature an option for ultra-low latency video encoding. This enables near-real time video transmission for streaming and wireless video applications, especially when coupled with CAST’s hardware stacks for fast, processor-less video processing.

Low Latency and Video Encoding
Latency is the delay incurred in processing and transmitting live video. Having a negligible delay of under 150 milliseconds (4.5 frames for 30 frames per second video) is critical in applications involving human interaction—such as video conferencing, remote surgery, online gaming, or high-value surveillance—and an even lower delay of 30ms (one frame for 30fps) or less is essential for many automotive, industrial, and medical systems.
While total latency is determined by the end-to-end process of video capture, encoding, transmission, decoding, and display, it is the encoding that typically has the most critical role. An ultra-low latency encoder needs to meet the target bit rate (e.g. 7 Mbps) over a small period of time (e.g. 1 frame). This allows the decoder to start the decoding process after buffering just a small amount of the compressed stream, and provides guarantees that the decoder buffer will not underflow throughout video playback.

Achieving Ultra-Low Latency Video Encoding
The H.264 video encoder cores available from CAST have always allowed a designer to regulate latency down to a few frames through a sophisticated rate control algorithm. The intra-only versions of these encoders can now go further, giving designers the ability to regulate latency at a deep sub-frame level. This enables latencies under 20ms for 30 frames per second video, and under 10ms for 60fps.
The sub-frame rate control feature for ultra-low latency is now a standard part of the intra-only version video encoder cores and available from CAST worldwide. These new ultra-low latency intra-only encoders support the Baseline, Main, and High Profiles of the H.264 standard (ISO/IEC 14496-10/ITU-T) and are sourced from technology partner Alma Technologies.

Video Streaming Hardware Stacks
Processing the encoded video stream for transmission also impacts end-to-end latency. Most video systems rely on a central system processor to handle this, but for many applications there is a quicker method.
Dedicated hardware stacks can more efficiently transmit video over specific channels. CAST has developed two such stacks that can prepare and transmit a video stream without the assistance of a processor: the UDP/IP Hardware Protocol Stack Core handles video transmission over an Ethernet LAN or similar Internet Protocol media, and the Hardware RTP Stack Core encapsulates H.264/NAL streams to Real-time Transport Protocol packets that are compliant with RFC 3894 and RFC 6184.
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